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Electronic Engineer: Integrated Circuit Design

Technical Consultant #889


High Performance Integrated Circuit Design

  • Chip Optimization

Second Sourcing - Power reduction, speed enhancement, returning to new process Reverse Engineering

  • IC Designs - ROMS, DRAMS/SRAMS, Compiler/ASIC, Macros, Analogue

Full CAD Facility In-House - HSPICE, Schematic Capture, Layout Extraction, Layout Editor, DRC, LVS, SPR

  • Topological Reviews
  • Radiation Analysis and Design - SEU, Transient, Total Dose

Multi-Chip System Interfacing

  • Memory Performance - Speed, Timing, Power
  • Memory/System Compatibility
  • Memory Radiation Performance

Electrical Process Characterization

  • Technologies - Unipolar MOSFETS, BulkCMOS, SOS/SOI
  • Radiation Specification and Testing
  • Spice Parametric Extraction
  • Electrical Specification of New Processes
  • Design Rule Evaluation - Critique, Develop, Optimize
  • Test Chip Generation
  • Consulting Engineer to Legal Profession
  • Expert witness in more than 30 patent litigations.


Advanced VLSI Design Group; Advanced Technology Labs of RCA/GE, Moorestown, NJ, Staff Engineer

  • Design and project responsibility 3-25ns CMOS SOS Radiation Hardened SRAMS
  • Generated CMOS SOS design rules (1.2) and process specification.
  • Modeled processes for "SPICE like" circuit simulation program.
  • Directed test chip generation and evaluation for Rad-Hard Process.
  • Advanced Memory Products, Solid State Scientific, Willow Grove, PA. Senior

Principal Engineer

  • Design and project responsibility for CMOS memory product line which included 13 IC's. Among those were a sub 100ns 256K CMOS ROM and 35ns 16K CMOS SRAM with 4 column redundancy.
  • Proposed and electrically specified the first 5v N-well double poly CMOS process.
  • Specified and designed process evaluation test chips and electrically modeled characteristics of the then State-Of-The-Art processes.
  • Initiated, enhanced, and supported MSINC (similar to SPICE) circuit simulation program.
  • Memory Products; M.O. S. Technology, Valley Forge, PA, Senior Engineer
  • Wrote CAD analysis program (ICCA) and characterized the P-channel and N-channel processes for same.
  • Design and project responsibility for five memory chip designs including 3 DRAMS.
  • Advanced Development Group; General Instrument Corp., Hicksville, L.I., NY,


  • Worked on design team of the first 256-bit DRAM
  • Solid State Device Dept; Bayside Research Labs of General Telephone and Electronics, NY, Engineer
  • Designed and developed circuits and subsystems suitable for integration.
  • Designs included MOS Multiplier and D/A converter.

Honors & Publications

  • 6 Granted patents, 12 Pending or applied for


  • M.S., Electrical Engineering, Clarkson University, 1964, Computer System Design
  • B.S., Electrical Engineering, Clarkson University, 1963, Computer Logic Design
  • Post graduate work, New York University, Drexel University
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