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Electrical and Computer Engineer: Embedded Systems, Computer Architecture, Smart Sensors, Wireless Systems and Low Power and VLSI

Technical Consultant #1881


  • Patent portfolio analysis and asset valuation for license or acquisition.
  • Patent infringement and claim chart development.
  • Low power technology; IC power management.
  • System on chip (ASIC) development; embedded systems and sensor and control systems.
  • RFID (Radio-Frequency Identification) systems development.
  • Computer and semiconductor architecture; computer arithmetic.
  • Chip design, analog and digital and VLSI.
  • Semiconductor memories: SRAM, ROM, MTP, EEPROM, EPROM, DDR, SD card, embedded flash.
  • Smart sensors; smart power meters; automatic meter reading (AMR).
  • Models for power supplies and LED lighting architectures.
  • Wireless systems; communication protocols: SPI, I2C, CAN.
  • Inventor with 24 issued patents.
  • Led chip development involving digital signal processors, micro controllers, A/D converters, digital filters, memory, interfaces, computer arithmetic and other peripherals for RFMicron, Cirrus Logic, Crystal Semiconductor, Infotronics, Intel and Honeywell. Areas of interest include:
    • Smart sensors
    • Embedded systems
    • Wireless systems
    • Memories (SRAM, ROM, EEPROM)
    • Systems on Chip (SoC)
    • Mobile computing
    • Computer architecture
    • Low power methodologies.

Expert Witness Experience

Assisting law firms and engineering companies in intellectual property matters which involve:

  • Asset valuation, claim chart development, expert witness depositions, prior art research and patent infringement analysis.
  • Leads engineering teams in the development of proprietary technologies and new products as part of ESST.


  • Intellectual property disputes: Semiconductors in bus architecture utilized in competitor's multicore product line, algorithms that were found in the manufacture of money counting products latest line, and intellectual property related to C++ and software defined networks.
  • Copyright infringement and patent infringement, alleging that defendant used plaintiff's technology in a new product, provided technical expert opinion on C++, object oriented programming and communication network matters.
  • For a Chicago law firm, led patent infringement analysis of an electronic sensor system.
  • For a Texas law firm, researched software of prior art for database systems implemented in C++ and Perl.


Undisclosed Company, Founder and CEO, 2011 - Present

Technical Expert consulting for law firms and technology companies in intellectual property issues:

  • Developed smart phone extender technology to use cell phone as a server and project to a tablet like monitor using Miracast technology.
  • Performed patent portfolio analysis and claim chart development for Secure Digital Card (SD Card) standard. Extensive analysis of digital camera technology, Video Recording, SD Card protocol and EEPROM/Flash technology. Extensive analysis of plug and play technology and software drivers.
  • Served as technical expert and completed asset valuation analysis on LED lighting patent portfolio.
  • Data mining of patent portfolio in the areas of: Computer architecture, mobile devices, servers and cloud computing.
  • Patent infringement analysis and claim chart development in mobile devices.


  • Claim chart development.
  • Technical analysis and asset valuation.
  • Technology, system on chip and system integration.
  • Embedded systems, mixed signal systems, semiconductor memories (SRAM, ROM, EEPROM), computer architecture, computer arithmetic, wireless architecture and protocols, IC power management and analog/digital VLSI.

RF Micron Inc., Austin, Texas, Vice President of Engineering, 2009 - 2011

  • Architected design flows, evaluated technology and selected the team to execute company's vision.
  • For clients, evaluated intellectual property in the following areas:
  • Asset valuation: Mixed signal, circuit design, memories; (SRAM, ROM, DRAM, EEPROM Flash), communication standards, communication systems, low power architectures, power supplies, computer architecture, Systems on Chip and I/O pads.
  • Performed asset valuation of technologies related to the following standards: SPI, USB, CAN, 802.11, EPC Gen II, NFC, DDR, UART and I2C.
  • Reviewed licensing terms, technology, and performed claim analysis.
  • Modeled algorithm in C language.
  • Coded digital architecture in Verilog, implemented chip level synthesis and performed top level simulations.
  • Developed and implemented architecture wireless protocol EPC Gen 2 Class I protocol of RFID systems.
  • Architected and implemented low power digital architecture to perform power management and optimize power consumption.
  • Integrated and designed a SPI interface for a NVM multiple times programmable memory module.

Cirrus Logic Inc., Austin, TX, Technical Lead, 1994 - 2008

System Engineer - Technical, 2003 - 2008

  • Led a group of engineers to research and develop models for power supplies and LED/lighting architectures using Simulink, Matlab and C.

Design Manager and Program Manager, Industrial Product Division, 2006 - 2008

  • Led a mixed-signal team of 12 in an 18 month project, implementing the first embedded flash memory, high performance analog ARM7 based energy measurement SoC. Taped out the chip ahead of time with first pass success.
  • Drove the architecture of next generation energy and power measurement system on a chip through integration of a 32-bit RISC ARM7 processor, SRAM, ROM, digital filters and a 24-bit delta sigma converter, RTC, band gap and multiple peripherals.
  • Served as Program Manager in charge of project schedule and resource allocation of the analog, digital, verification, product and test teams.
  • Collaborated with marketing team to define product specification and develop roadmap.
  • Put in place a mixed-signal based design flow using ADMS and ModelSim.
  • Supervised submission of Memorandum of Inventions (MOIs) from the team, patent preparation and performed claim analysis before patent submission.
  • Designed flash memory (NVM) interface and patented flash locking mechanism.
  • Designed serial port interface and evaluated SD card protocol.
  • Responsible for IP purchase and integration: Evaluated and licensed intellectual property.
  • Researched and analyzed integration of Zigbee, power line communications and other protocols for smart power meters.
  • Architected and coordinated the evaluation of the architecture using FPGA board.
  • Wrote system architecture document, technical specification and led documentation of test plans, architecture reviews and design reviews.
  • Led the software team and coordinated scope and tasks definition.
  • Successfully passed two ISO9001 audits for the project.
  • Supervised design, test and characterization of the LCD interface.
  • Successfully passed two ISO9001 audits for the project.

Staff Engineer, Embedded Processor Division, 2003 - 2006

Key member of technical staff in the multimedia product group trusted with the design of critical blocks like video engine, DDR II interface and new micro controller based architectures for industrial applications.

  • Led design of a DDR memory interface and integrated this unit with multiple bank buffer graphic engine architecture.
  • The graphic engine was part of an ARM9 multimedia System on a Chip in 0.18µm technology.
  • Studied and analyzed graphic engine pipeline to achieve peak performance in an ARM9 multimedia SoC.
  • Designed DDR memory interface and DLL in 0.18µm. Modeled the system in Matlab.
  • Implemented the DDR unit controller in Verilog.
  • Performed circuit design of DLL in Cadence and simulated in Hspice.
  • Product became a pioneer in the audio/video set-top multimedia market.
  • Led architecture and technical specification of micro controller based project for industrial applications.
  • Architected and designed a PWM unit for motor control.
  • Debugged a 14-bit A/D in an ARM9 general purpose SoC in 0.18µm technology.
  • Debugged Real time clock noise issues and pads.

Design Manager, Data Acquisition Division, 1999 - 2001

  • Designed and directed mixed signal system on chip, incorporating ARM7-based processors, Flash memory (NVM), Ethernet 10/100 and A/D plus peripherals for industrial applications.
  • Researched and recommended a smart sensor architecture integrating high performance analog, ARM7 processors and communication peripherals like CAN, SPI or ethernet.
  • Led verification effort of a S/PDIF controller for a Codec product in the audio division.
  • Served as a Teaching Assistant in the System Design and Modeling graduate course taught by Eric Swanson at University of Texas at Austin.

Project Manager, Data Acquisition Division, 1997 - 1999

  • Implemented and synthesized digital filters, main controller and clock generator in Verilog and Synopsys.
  • Conducted design reviews and supervised layout and tape-out of chips.
  • Established company's dominant position in $5 million to $10 million annual industrial weight scale market by leading design and implementation of 24 bit A/D 130nVpp chip for high performing A/Ds.
  • Selected as Technical Committee Member for Innovative Systems on Silicon.
  • Chosen as Technical Committee Member for International Conference on computer design.

Staff Engineer, Data Acquisition Division, 1996 - 1997

  • Led the IC power management effort to minimize power dissipation for a digital signal processing ASIC and a new telemetry communication system used in seismic exploration.
  • Analyzed clock networks using Arcadia and Hspice to calculate and minimize clock skew in a 0.35µm ASIC.
  • Performed chip top level simulations for power, timing and critical path delays using TimeMill, PowerMill and PathMill.
  • Designed SRAMs, ROM, parallel multiplier and switching regulator for low voltage generation.
  • Developed centerpiece for $10 million market by directing completion of ASIC for seismic applications.

Design Engineer, Data Acquisition Division, 1994 - 1996

  • Patented and developed high speed low power parallel multiplier. Implemented design in a test chip.
  • Led development of low-power RAM generator, used in 2 generations of seismic chips.

Independent Consultant, Technical Expert, 2001 - 2003


  • Jenkens & Gilchrist, Chicago, IL: Led patent infringement analysis of an electronic sensor system.
  • Performed patent analysis and reverse engineering of the system.
  • Brobeck, Phleger & Harrison, Austin, TX: Researched software of prior art for database systems implemented in C++ and Perl.
  • Infotronic, Austin, TX: Reviewed and developed 0.25µm ASIC design flow for an ARM9 processor plus peripherals on a chip. Developed contracts with IC vendors and reviewed technical specifications.

Intel Inc., Santa Clara, CA, Graduate Rotation Engineer, Quality and Reliability Division, 1993

  • Debugged a wire up board and designed a new board system to automatically perform IDDQ testing of SRAM memories of x386 microprocessor architecture using PAL/PLD blocks.

Honeywell, Inc., Phoenix AZ, Engineer, Avionic and LCD Panels Division, 1991

  • Designed LCD drivers: Performed circuit design at the transistor level and optimized layout and power dissipation in CMOS/NMOS technology.

Alcoa Inc., Pittsburg, PA, Intern Engineer, 1989

  • Debugged and wrote programs in FORTRAN to model multiple aluminum processes.

Honors & Publications


  • Expert Witness Boot Camp: Rigorous training on expert witness depositions and trial direct/cross examinations.
  • Professional Engineer licensed Texas
  • Project Management Professional
  • Program Evaluator, ABET (Accreditation Board for Engineering and Technology)
  • Dissertation: Low Power Digital Multiplication
  • Focused Studies: CMOS Analog, Digital VLSI Design, Advanced VLSI, Fast Fourier Transforms, Semiconductor Fabrication, High Frequency Design and Bipolar Analog Design.


  • Spanish: Speaking-fluent, conversation, writing

Academic and Professional Affiliations

  • Institute of Electrical and Electronics Engineers (IEEE), Senior Member
  • Board Member at Life Changers
  • Toastmaster Member


  • Phi Kappa Phi
  • Tau Beta Pi
  • GEM Fellowship

Publications and Patents

  • Author of numerous publications in national and International conferences, symposiums, journals and newsletters.
  • Over 20 patents.


  • Ph.D. Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX
  • M.S. Electrical Engineering, Stanford University, Palo Alto, CA
  • B.S. Electrical Engineering, (Magna cum Laude), University of Puerto Rico, Mayaguez, P. R.
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